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SPARCstation 10


Aliases  
Date  
CPUs 1 - 4
Clock speed 33, 36, 40, 50, 60, 75, 90, 125, 150, 180 MHz
Processor Mbus SPARCmodule   (microSPARC, hyperSPARC)
Co-processor  
MMU  
Motherboard  
On-chip cache  
External cache Up to 1 MB / Mbus module.
Memory 512 MB
16 MB or 64 MB 70ns SIMMs.
Speed @ 33 MHz:   39.8 SPECint92,   46.6 SPECfp92,   943 SPECintRate92,   1104 SPECfpRate92
@ 36 MHz:   45.2 SPECint92,   54.0 SPECfp92,   1072 SPECintRate92,   1282 SPECfpRate92
@ 40 MHz:   50.2 SPECint92,   60.2 SPECfp92,   1191 SPECintRate92,   1427 SPECfpRate92
@ 40 MHz (x2):   2112 SPECintRate92,   2378 SPECfpRate92
@ 40 MHz + 1 MB:   53.2 SPECint92,   67.8 SPECfp92,   1264 SPECintRate92,   1607 SPECfpRate92
@ 40 MHz + 1 MB (x2):   2411 SPECintRate92,   2854 SPECfpRate92
@ 50 MHz + 1 MB:   65.2 SPECint92,   83.0 SPECfp92,   1580 SPECintRate92,   2008 SPECfpRate92
@ 50 MHz + 1 MB (x2):   2950 SPECintRate92,   3744 SPECfpRate92
@ 50 MHz + 1 MB (x4):   5155 SPECintRate92,   5809 SPECfpRate92
Chassis type pizzabox
Bus (2) Mbus slots.
(4) Sbus slots:   16.6 / 20 MHz (model 20) or 18 / 20 MHz
Ports  
Internal storage Built in 1.44 MB 3.5" floppy.
Graphics  
Power supply  
Architecture sun4m
OS's supported  
Notes Code name "Campus-2".
Comments  
See also..  


























































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   Last modified: 2002.01.14.07.39.35 CST
     Server time: 2017.03.26.20.52.45 GMT