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• Specifications

100U, 2/120, 2/170 CPU Multibus

 10MHz 68010, no floating point chip, MMU, no on-board memory.  Multibus
  interface.

 The CPU board is entirely concealed within the chassis. On one long edge, it
  has Multibus card-edge connectors. On the other long edge, from top to
  bottom, it has: a header connector for the Sun-1 parallel keyboard and mouse,
  eight LEDs, and a 50-pin header connector (J1) for two serial ports.

 The LEDs display the usual sort of test cycling at power-up.  Unlike later
  models, they do not simply blink or cylon while the OS is running; instead,
  they display all sorts of patterns, possibly in response to bus activity (?).

 Jumper information:

 J200    Crystal shunt                           JUMPED by default
  Located by crystal at D1.
  Removed for A.T.E. testing, installed for normal operation.

 J400    EPROM select                            JUMPED by default
  Located by EPROMs at D10.
  1-2   selects 27128 EPROMs (default)
  3-4   selects 27256 EPROMs

 J700    Bus priority on serial arbitration      UNJUMPED by default
  Located by bus connectors.

 J701    Common bus request arbiter              UNJUMPED by default
  Located by bus connectors.
  If the CPU board is used in conjunction with a Multibus DMA board (such as a
   disk or tape controller) that does NOT support the Common Bus Request
   (CBRQ), the CPU board must be configured such that it gives up the Multibus
   after every Multibus cycle, by jumping J701.  This also causes three
   additional wait states for each Multibus access.  When this jumper is
   unjumped, the CPU board retains bus mastership until a lower priority master
   requests it by asserting CBRQ.  Following a CBRQ, the CPU board yields
   mastership for at least one cycle.  Certain machine configurations
   (especially those with color) will be much slower if this jumper is jumped.

 J702    Enables the CCLK on P1  JUMPED by default
  Located by bus connectors.

 J703    Enables the BCLK on P1  JUMPED by default
  Located by bus connectors.

 J801    Selects +5V for the parallel mouse      UNJUMPED by default
  Located by J2 header connector.
  Used only in 100U configurations (?).

 The two serial ports on J1 are usually labelled SIO-A and SIO-B on the back of
  the machine and appear as /dev/ttya and /dev/ttyb under SunOS.  The
  documented maximum output speed is 19200 bps.  All ports are wired DTE and
  are compatible with both RS-232C and RS-423, using Zilog Z8530A dual UART
  chips.  The pinout of J1 is:

  3    TxD-A       14  DTR-A       33  DD-B
  4    DB-A        15  DCD-A       34  CTS-B
  5    RxD-A       22  DA-A        36  DSR-B
  7    RTS-A       24  BSY-A       38  GND-B
  8    DD-A        28  TxD-B       39  DTR-B
  9    CTS-A       29  DB-B        40  DCD-B
  11   DSR-A       30  RxD-B       47  DA-B
  13   GND-A       32  RTS-B       49  BSY-B

 Power requirements are +5V @ 6A.

  

   Last modified: 2000.11.05.19.23.53 CST
     Server time: 2010.07.30.08.30.16 GMT